AD80066KRSZ(RevA) 데이터 시트보기 (PDF) - Analog Devices

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AD80066KRSZ
(Rev.:RevA)

Complete 16-Bit CCD/CIS Signal Processor

Analog Devices 

THEORY OF OPERATION

The AD80066 can be operated in several different modes,

including 4-channel CDS mode, 4-channel SHA mode, 1-channel

CDS mode, and 1-channel SHA mode. Each mode is selected

by programming the configuration register through the serial

interface. For more information on CDS or SHA mode operation,

see the Circuit Operation section.

4-CHANNEL CDS MODE

In 4-channel CDS mode, the AD80066 simultaneously samples

the A, B, C, and D input voltages from the CCD outputs. The

sampling points for each CDS are controlled by CDSCLK1 and

CDSCLK2 (see Figure 17 and Figure 18). The CDSCLK1 falling

edge samples the reference level of the CCD waveform, and the

CDSCLK2 falling edge samples the data level of the CCD wave-

form. Each CDS amplifier outputs the difference between the

CCD reference level and the data level. The output voltage of

each CDS amplifier is then level-shifted by an offset DAC. The

voltages are scaled by the four PGAs before being multiplexed

through the 16-bit ADC. The ADC sequentially samples the

PGA outputs on the falling edges of ADCCLK.

The offset and gain values for the A, B, C, and D channels are

programmed using the serial interface. The order in which the

channels are switched through the multiplexer is selected by

programming the mux register.

Timing for this mode is shown in Figure 3. The falling edge of

CDSCLK2 should occur coincident with or before the rising

edge of ADCCLK. However, this is not required to satisfy the

minimum timing constraints. The rising edge of CDSCLK2

should not occur before the previous falling edge of ADCCLK,

as shown by tADC2. The output data latency is 3 ADCCLK cycles.

4-CHANNEL SHA MODE

In 4-channel SHA mode, the AD80066 simultaneously samples

the A, B, C, and D input voltages. The sampling point is controlled

by CDSCLK2. The falling edge of CDSCLK2 samples the input

waveforms on each channel. The output voltages from the three

AD80066

SHAs are modified by the offset DACs and then scaled by the

four PGAs. The outputs of the PGAs are then multiplexed

through the 16-bit ADC. The ADC sequentially samples the

PGA outputs on the falling edges of ADCCLK.

The input signal is sampled with respect to the voltage applied to

the OFFSET pin (see Figure 19). With the OFFSET pin grounded,

a 0 V input corresponds to the zero-scale output of the ADC.

The OFFSET pin can also be used as a coarse offset adjustment

pin. A voltage applied to this pin is subtracted from the voltages

applied to the A, B, C, and D inputs in the first amplifier stage

of the AD80066. The input clamp is disabled in this mode. For

more information, see the Analog Inputs—SHA Mode section.

The offset and gain values for the A, B, C, and D channels are

programmed using the serial interface. The order in which the

channels are switched through the multiplexer is selected by

programming the mux register.

Timing for this mode is shown in Figure 7. The CDSCLK1 pin

should be grounded in this mode. Although not required, the

falling edge of CDSCLK2 should occur coincident with or before

the rising edge of ADCCLK. The rising edge of CDSCLK2 should

not occur before the previous falling edge of ADCCLK, as shown

by tADC2. The output data latency is 3 ADCCLK cycles.

1-CHANNEL CDS MODE

The 1-channel CDS mode operates in the same way as the

4-channel CDS mode, except the multiplexer remains fixed.

Only the channel specified in the mux register is processed.

Timing for this mode is shown in Figure 6.

1-CHANNEL SHA MODE

The 1-channel SHA mode operates in the same way as the

4-channel SHA mode, except the multiplexer remains fixed.

Only the channel specified in the mux register is processed.

Timing for this mode is shown in Figure 8. The CDSCLK1 pin

should be grounded in this mode of operation.

Rev. A | Page 13 of 20

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