AD8352 데이터 시트보기 (PDF) - Analog Devices
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AD8352 Datasheet PDF : 19 Pages
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Data Sheet
VCC
IF/RF INPUT
0.1µF
0Ω 16
1
2
ADT1-1WT
50Ω
RD
RG
CD
3
4
0.1µF
5
0Ω
0.1µF
8, 13
11 0.1µF 24Ω
AD8352
AD9445
10 0.1µF 24Ω
14
0.1µF
Figure 34. Differential Input to the AD8352 Driving the AD9445
0.1µF
VIP
VOP 0.1µF 33Ω
50Ω 50Ω
AC
CD RD RG
VIN
25Ω 0.1µF
RN
200Ω
AD8352
33Ω
VON 0.1µF
VIN+
AD9445
VIN–
Figure 35. Single-Ended Input to the AD8352 Driving the AD9445
0
–10
SNR = 67.26dBc
SFDR = 83.18dBc
–20
NOISE FLOOR = –110.5dB
FUND = –1.074dBFS
–30
SECOND = –83.14dBc
–40
THIRD = –85.39dBc
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 36. Single Tone Distortion AD8352 Driving AD9445,
Encode Clock at 105 MHz with fC at 100 MHz (AV = 10 dB), See Figure 34
AD8352
0
SNR = 61.98dBc
–10
NOISE FLOOR = –111.2dB
–20
FUND1 = –7.072dBFS
FUND2 = –7.043dBFS
–30
IMD (2F2-F1) = –89dBc
–40
IMD (2F1-F2) = –88dBc
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 37. Two Tone Distortion AD8352 Driving AD9445,
Encode Clock at 105 MHz with fC at 100 MHz (AV = 10 dB),
Analog In = 98 MHz and 101 MHz, See Figure 34
LAYOUT AND TRANSMISSION LINE EFFECTS
High Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies resulting
in excessive gain peaking or possible oscillation. If RF transmission
lines connecting the input or output are used, they should be
designed such that stray capacitance at the input/output pins is
minimized. In many board designs, the signal trace widths should
be minimal where the driver/ receiver is more than one-eighth
of the wavelength from the AD8352. This nontransmission line
configuration requires that underlying and adjacent ground and
low impedance planes be dropped from the signal lines. In a
similar fashion, stray capacitance should be minimized near the
RG, CD, and RD components and associated traces. This also
requires not placing low impedance planes near these components.
Refer to the evaluation board layout (Figure 39 and Figure 40)
for more information. Excessive stray capacitance at these nodes
results in unwanted high frequency distortion. The 0.1 µF supply
decoupling capacitors need to be close to the amplifier. This
includes Signal Capacitor C2 through Signal Capacitor C5.
Parasitic suppressing resistors (R5, R6, R7, and R11) can be
used at the device input/output pins. Use 25 Ω series resistors
(Size 0402) to adequately de-Q the input and output system
from most parasitics without a significant decrease in gain. In
general, if proper board layout techniques are used, the suppression
resistors are not necessarily required. Output Parasitic Suppression
Resistor R7 and Output Parasitic Suppression Resistor R11 can
be required for driving some switch capacitor ADCs. These
suppressors, with Input C of the converter (and possibly added
External Shunt C), help provide charge kickback isolation and
improve overall distortion at high encode rates.
Rev. C | Page 15 of 19
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