AD9139(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD9139 Datasheet PDF : 56 Pages
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AD9139
Data Sheet
detected. The compare fail bit is automatically cleared by the
reception of eight consecutive error free comparisons when
autoclear mode is enabled.
The sample error flag can be configured to trigger an IRQ when
active, if desired, by enabling the appropriate bit in the event
flag register (Register 0x04, Bit 6).
SED EXAMPLE
Normal Operation
The following example illustrates the AD9139 SED configuration
for continuously monitoring the input data and assertion of
an IRQ when a single error is detected.
1. Write to the following registers to enable the SED and load
the comparison values with a four-deep user pattern.
Comparison values can be chosen arbitrarily; however,
choosing values that require frequent bit toggling provides
the most robust test.
a. Register 0x61[7:0]→ S0[7:0]
b. Register 0x62[7:0]→ S0[15:8]
c. Register 0x63[7:0]→ S1[7:0]
d. Register 0x64[7:0]→ S1[15:8]
e. Register 0x65[7:0]→ S2[7:0]
f. Register 0x66[7:0]→ S2[15:8]
g. Register 0x67[7:0]→ S3[7:0]
h. Register 0x68[7:0]→ S3[15:8]
2. Enable SED.
a. Register 0x60 → 0xD0
b. Register 0x60 → 0x90
3. Enable the SED error detect flag to assert the IRQx pin.
a. Register 0x04[6] = 1
4. Begin transmitting the input data pattern (FRAMEx is also
required because the depth of the pattern is 4).
DELAY LINE INTERFACE MODE
The DLL is designed to help ease the interface timing require-
ments in very high speed data rate applications. The DLL has
a minimum supported interface speed of 250 MHz, as shown
in Table 2. For interface rates below this speed, use the interface
delay line. In this mode, the DLL is powered off and a four-tap
delay line is provided for the user to adjust the timing between
the data bus and the DCI. Table 15 specifies the setup and hold
times for each delay tap.
Table 15. Delay Line Setup and Hold Times (Guaranteed)
Delay Setting
0
1
2
3
Register 0x5E[7:0]
0x00 0x80 0xF0 0xFE
Register 0x5F[2:0]
0x60 0x67 0x67 0x67
tS (ns)1
−0.81 −0.97 −1.13 −1.28
tH (ns)
1.96 2.20 2.53 2.79
|tS + tH| (ns)
1.15 1.23 1.40 1.51
1 The negative sign indicates the direction of the setup time. The setup time is
defined as positive when it is on the left side of the clock edge and negative
when it is on the right side of the clock edge.
There is a fixed 1.38 ns delay on the DCI signal when the delay line
is enabled. Each tap adds a nominal delay of 200 ps to the fixed
delay. To achieve the best timing margin, that is, to center the
setup and hold window in the middle of the data eye, the user
may need to add a delay on the data bus with respect to the DCI
signal in the data source. Figure 33 is an example of calculating
the optimal external delay.
Register 0x0D[4] configures the DCI signal coupling settings
for optimal interface performance over the operating frequency
range. It is recommended that this bit be set to 1 (dc-coupled
DCI) in the delay line interface mode.
tDELAY = 0.13ns
tDATA PERIOD = 2.5ns
INPUT DATA[15:0]
WITH
OPTIMIZED DELAY
|tS| = 0.81ns
|tH| = 1.96ns
DATA EYE
DCI = 200MHz
NO DATA TRANSITION
Figure 33. Example of Interfacing Timing in the Delay Line-Based Mode
Rev. 0 | Page 22 of 56
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