AD9250 데이터 시트보기 (PDF) - Analog Devices
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AD9250 Datasheet PDF : 45 Pages
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Data Sheet
AD9250
The output common-mode voltage of the ADA4930-2 is easily
set with the VCM pin of the AD9250 (see Figure 39), and the
driver can be configured in a Sallen-Key filter topology to
provide band-limiting of the input signal.
15pF
VIN
76.8Ω
0.1µF
200Ω
90Ω
33Ω
15Ω
5pF
ADA4930-2
120Ω
200Ω
33Ω
15Ω
15pF
VIN– AVDD
ADC
VIN+
VCM
33Ω
0.1µF
Figure 39. Differential Input Configuration Using the ADA4930-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 40. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
2V p-p
49.9Ω
C2
R3
R2
VIN+
R1
C1
ADC
R1
R2
VIN–
VCM
0.1µF
R3
33Ω
C2
0.1µF
Figure 40. Differential Transformer-Coupled Configuration
Consider the signal characteristics when selecting a transformer.
Most RF transformers saturate at frequencies below a few
megahertz. Excessive signal power can also cause core saturation,
which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9250. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 41). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
2V p-p
0.1µF
PA
SS
0.1µF
P
0.1µF
33Ω
33Ω
C2
R3
R1
R2
C1
0.1µF
R1
R2
R3
C2
VIN+
ADC
VIN–
VCM
33Ω
0.1µF
Figure 41. Differential Double Balun Input Configuration
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Table 9 are for each
R1, R2, C1, C2, and R3 components shown in Figure 40 and
Figure 41.
Table 9. Example RC Network
Frequency R1
Range
Series
(MHz)
(Ω)
C1
Differential
(pF)
0 to 100 33
8.2
100 to 400 15
8.2
>400
15
≤3.9
R2
Series
(Ω)
0
0
0
C2
Shunt
(pF)
15
8.2
≤3.9
R3
Shunt
(Ω)
24.9
24.9
24.9
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGAs) provides good performance for driving the AD9250.
Figure 42 shows an example of the AD8376 driving the AD9250
through a band-pass antialiasing filter.
1000pF 180nH 220nH
1µH
AD8376
1µH
VPOS
165Ω
5.1pF 3.9pF
1nF 301Ω
165Ω
15pF
VCM
1nF
ADC
20kΩ║2.5pF
68nH
NOTES
1000pF 180nH 220nH
1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE
EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Figure 42. Differential Input Configuration Using the AD8376
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9250.
The full-scale input range can be adjusted by varying the reference
voltage via the SPI. The input span of the ADC tracks the reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
The AD9250 has two options for deriving the input sampling
clock, a differential Nyquist sampling clock input or an RF clock
input (which is internally divided by 4). The clock input is selected
in Register 0x09 and by default is configured for the Nyquist clock
input. For optimum performance, clock the AD9250 Nyquist
sample clock input, CLK+ and CLK−, with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 43) and require no external bias. If the clock inputs
are floated, CLK− is pulled slightly lower than CLK+ to prevent
spurious clocking.
Rev. E | Page 21 of 45
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