AD9653-125EBZ 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD9653-125EBZ

Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter

Analog Devices 

Data Sheet

TIMING SPECIFICATIONS

Table 7.

Parameter

SYNC TIMING REQUIREMENTS

tSSYNC

tHSYNC

SPI TIMING REQUIREMENTS

tDS

tDH

tCLK

tS

tH

tHIGH

tLOW

tEN_SDIO

tDIS_SDIO

Description

SYNC to rising edge of CLK+ setup time

SYNC to rising edge of CLK+ hold time

See Figure 75

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an output relative to the

SCLK falling edge (not shown in Figure 75)

Time required for the SDIO pin to switch from an output to an input relative to the

SCLK rising edge (not shown in Figure 75)

AD9653

Limit Unit

0.24 ns typ

0.40 ns typ

2

ns min

2

ns min

40

ns min

2

ns min

2

ns min

10

ns min

10

ns min

10

ns min

10

ns min

Timing Diagrams

Refer to the Memory Map Register Descriptions section and Table 23 for SPI register settings.

VIN±x

CLK–

CLK+

DDR

DCO–

DCO+

SDR DCO

FCO–

BITWISE

MODE

FCO+

D0–A

D0+A

D1–A

D1+A

FCO–

BYTEWISE

MODE

FCO+

D0–A

D0+A

D1–A

D1+A

N–1

tA

tEH

tCPD

N

tEL

N+1

tFCO

tPD

tFRAME

tDATA

D14 D12 D10 D08 D06 D04 D02 LSB D14 D12 D10 D08 D06 D04 D02 LSB

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16

MSB

N – 17

D13

N – 17

D11

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

tLD

D01 MSB

N – 17 N – 16

D13

N – 16

D11

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

D07 D06 D05 D04 D03 D02 D01 LSB D07 D06 D05 D04 D03 D02 D01 LSB

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16

MSB D14 D13 D12 D11 D10 D09 D08 MSB D14 D13 D12 D11 D10 D09 D08

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16

Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)

Rev. 0 | Page 9 of 40

Share Link: