AD9816 데이터 시트보기 (PDF) - Analog Devices
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AD9816 Datasheet PDF : 16 Pages
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AD9816
RED
PGA
GREEN
PGA
PGAOUT_T
PGAOUT_C
3:1
DIFF
MUX
12-BIT ADC
Analog-to-Digital Converter
The AD9816 uses a high speed 12-bit ADC core. This CMOS
converter is designed to run at 6 MSPS with good linearity and
noise performance. Figure 19 shows the INL and DNL perfor-
mance of a typical AD9816 device, running at 6 MHz in 3-channel
CDS mode using the timing shown in Figure 1. The following
timing parameters were used: tCRA = 500 ns, tADCLK = 83 ns,
tC1 = 20 ns, tC1C2 = 170 ns, tC1 = 80 ns, tADC2 = 3 ns, tC2AD = 83 ns,
and tC2C1 = 230 ns.
SELECT
The digital outputs of the AD9816 follow a straight binary
BLUE
PGA
2
MUX
CONTROL
ADCCLK
CDSCLK2
coding scheme. Table VI shows the digital output coding for
the 3 V input span.
OBSOLETE Figure 17. PGA/MUX Circuit Configuration
ANALOG
INPUTS
PIXEL n
BLUE
GREEN
RED
CDSCLK2
ADCCLK
PGAOUT_T
PGAOUT_C
GREEN(n–1)
RESET RED(n)
GREEN(n)
RESET
BLUE(n–1)
BLUE(n)
4.25V
3.5V
2.75V
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.2
–1.4
–1.6
0
1.5
MAX INL 0.18
MIN INL –1.46
400 800 1200 1600 2000 2400 2800 3200 3600 4095
1.0
MAX DNL 0.31
MIN DNL –0.33
0.5
0.0
–0.5
–1.0
0
400 800 1200 1600 2000 2400 2800 3200 3600 4095
Figure 19. Typical Linearity Performance
Table VI. Digital Output Format
Figure 18. PGA Output Voltages (ADC Input Range = 3 V)
Input Voltage1
Digital Outputs
Table V. Voltage Swing of PGA Outputs
3.0 – 1 LSB
1111 1111 1111
Analog
Differential
3.0 – 2 LSB
1111 1111 1110
Input
Voltage1
ADC
PGAOUT_T PGAOUT_C Input
0.0 + 1 LSB
0.0
0000 0000 0001
0000 0000 0000
0.002
1.502
3.002
0.003
0.753
1.503
2.75
3.50
4.25
3.125
3.50
3.875
4.25
3.50
2.75
3.875
3.50
3.125
1.5
0.0
+1.5
0.75
0.0
+0.75
NOTE
1Analog input voltage in CDS mode is the difference between the
CCD’s reference and data levels.
NOTES
1Analog input voltage in CDS mode is the difference between the CCD’s refer-
ence and data levels.
23.0 V Input Range.
31.5 V Input Range.
REV. A
–13–
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