AD9929 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD9929 Datasheet PDF : 64 Pages
| |||
AD9929
ADDRESS [7:0]
NUMBER WRITES N [23:0]
DATA 1 [31:0]
DATA 2 [31:0]
DATA N [31:0]
SDATA
SCK
SL
8 BIT ADDRESS
NUMBER OF 32 BIT
DATA WRITES (N)
DATA 1 [31:0]
1
DATA 2 [31:0]
DATA N [31:0]
1
12
NOTES
1. SL PULSES ARE IGNORED UNTIL THE LSB BIT OF THE LAST DATA N WORD IS CLOCKED IN.
2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.
Figure 11. System and Mode Register Writes
OPERATION OF VD SYNCHRONOUS
TYPE REGISTER WRITES BEGIN AT
THE NEXT VD FALLING EDGE.
VD
HD
CLI
PROGRAMMING VD SYNCHRONOUS
TYPE REGISTERS MUST BE
COMPLETED AT LEAST 4 CLI
CYCLES BEFORE THE FALLING
EDGE OF VD
Figure 12. VD Synchronous Type Register Writes
VD Synchronous and Asynchronous Register Operation
There are two types of control registers, VD synchronous and
VD asynchronous, as indicated in the address column of
Table 8. Register writes to synchronous and asynchronous
registers operate differently, as described in the following
sections. All writes to system Mode_A and Mode_B registers
occur asynchronously.
Asynchronous Register Operation
For VD asynchronous register writes, SDATA data is stored
directly into the serial register at the rising edge of SL. As a
result, register operation begins immediately after the rising
edge of SL.
VD Synchronous Register Operation
For VD synchronous registers, SDATA data is temporarily
stored in a buffer register at the rising edge of SL. This data is
held in the buffer register until the next falling edge of VD is
applied. Once the next falling edge of VD occurs, the buffered
SDATA data is loaded into the serial register, at which time the
register operation begins. See Figure 12.
All control registers at the following addresses are VD synchro-
nous type registers: Addresses 0x0A, 0x0B, 0x0C, 0x0D, and
0x0E. Also see Table 8, the Control Register Address Map.
Rev. A | Page 21 of 64
Share Link: 