AD9948 데이터 시트보기 (PDF) - Analog Devices

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AD9948

10-Bit CCD Signal Processor with Precision Timing™ Core

Analog Devices 

AD9948

TERMINOLOGY

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus every

code must have a finite width. No missing codes guaranteed to

10-bit resolution indicates that all 1024 codes, respectively,

must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the

peak deviation of the output of the AD9948 from a true straight

line. The point used as zero scale occurs 0.5 LSB before the

first code transition. Positive full scale is defined as a level 1 LSB

and 0.5 LSB beyond the last code transition. The deviation is

measured from the middle of each particular output code to the

true straight line. The error is then expressed as a percentage of

the 2 V ADC full-scale signal. The input signal is always appro-

priately gained up to fill the ADC’s full-scale range.

Total Output Noise

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated in

LSB, and represents the rms noise level of the total signal chain

at the specified gain setting. The output noise can be converted

to an equivalent voltage, using the relationship

1 LSB = (ADC full scale/2n codes)

where n is the bit resolution of the ADC. For the AD9948,

1 LSB is approximately 1.95 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply

pins. The PSR specification is calculated from the change in the

data outputs for a given step change in the supply voltage.

EQUIVALENT CIRCUITS

AVDD

DVDD

R

AVSS

AVSS

Circuit 1. CCDIN (Pin 27)

AVDD

330⍀ 25k⍀

CLI

1.4V

DATA

AVSS

Circuit 2. CLI (Pin 25)

DVSS

DRVDD

THREE-

STATE

DOUT

330⍀

DVSS

Circuit 4. Digital Inputs (Pins 31–35, 38)

HVDD or RGVDD

DATA

ENABLE

OUTPUT

HVSS or RGVSS

Circuit 5. H1–H4 and RG (Pins 14, 15, 18, 19, 21)

DVSS

DRVSS

Circuit 3. Data Outputs D0–D9 (Pins 2–4, 7–13)

–6–

REV. 0

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