AD9992 데이터 시트보기 (PDF) - Analog Devices

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AD9992

12-Bit CCD Signal Processor with Precision Timing Generator

Analog Devices 

AD9992

SYSTEM OVERVIEW

Figure 12 shows the typical system block diagram for the AD9992

in master mode. The CCD output is processed by AD9992 AFE

circuitry, which consists of a CDS, VGA, black level clamp, and

ADC. The digitized pixel information is sent to the digital

image processor chip, which performs the postprocessing and

compression. To operate the CCD, all CCD timing parameters

are programmed into the AD9992 from the system microprocessor

through the 3-wire serial interface. The AD9992 generates the

CCD’s horizontal and vertical clocks and internal AFE clocks

from the master clock, CLI, which is provided by the image

processor or external crystal,. External synchronization is provided

by a sync pulse from the microprocessor, which resets the

internal counters and resyncs the VD and HD outputs.

V-DRIVER

XV1 TO XV24, XSUBCK

H1 TO H8, HL,

RG

CCD

CCDIN

GPO1 TO GPO8

AD9992

AFETG

DOUT

DCLK

HD, VD

CLI

DIGITAL

IMAGE

PROCESSING

ASIC

SERIAL

INTERFACE

SYNC

MICROPROCESSOR

Figure 12. Typical System Block Diagram, Master Mode

Alternatively, the AD9992 can operate in slave mode. In slave

mode, the VD and HD are provided externally from the image

processor, and all AD9992 timing synchronizes with VD and HD.

H-drivers for H1 to H8, HL, and RG are included in the AD9992,

allowing these clocks to be directly connected to the CCD.

An H-driver voltage of up to 3.3 V is supported. An external

V-driver is required for the vertical transfer clocks, the sensor

gate pulses, and the substrate clock.

The AD9992 includes programmable general-purpose outputs

(GPO), which can trigger mechanical shutter and strobe (flash)

circuitry.

Figure 13 and Figure 14 show the maximum horizontal and

vertical counter dimensions for the AD9992. All internal

horizontal and vertical clocking is controlled by these counters,

which specify line and pixel locations. Maximum HD length

is 8192 pixels per line; maximum VD length is 8192 lines per field.

MAXIMUM COUNTER DIMENSIONS

13-BIT HORIZONTAL = 8192 PIXELS MAX

13-BIT VERTICAL = 8192 LINES MAX

Figure 13. Vertical and Horizontal Counters

MAX VD LENGTH IS 8192 LINES

VD

MAX HD LENGTH IS 8192 PIXELS

HD

CLI

Figure 14. Maximum VD/HD Dimensions

Rev. C | Page 14 of 92

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