ADM1032 데이터 시트보기 (PDF) - Analog Devices
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ADM1032 Datasheet PDF : 12 Pages
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ADM1032–SPECIFICATIONS (TA = TMIN to TMAX, VDD = VMIN to VMAX, unless otherwise noted.)
Parameter
Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage, VDD
Average Operating Supply Current, ICC
Undervoltage Lockout Threshold
Power-On Reset Threshold
3.0 3.30 5.5 V
170 215 µA
5.5 10
µA
2.35 2.55 2.8 V
1
2.4 V
0.0625 Conversions/Sec Rate1
Standby Mode
VDD Input, Disables ADC, Rising Edge
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
±1
±3
°C
Resolution
1
°C
Remote Diode Sensor Accuracy
±1
°C
±3
°C
Resolution
0.125
°C
Remote Sensor Source Current
230
µA
13
µA
Conversion Time
35.7
142.8 ms
5.7
22.8 ms
0 ≤ TA ≤ 100°C, VCC = 3 V to 3.6 V
60°C ≤ TD ≤ 100°C, VCC = 3 V to 3.6 V
0°C ≤ TD ≤ 120°C
High Level, Note 2
Low Level, Note 2
From Stop Bit to Conversion Complete
(Both Channels) One-Shot Mode with
Averaging Switched On
One-Shot Mode with Averaging Off
(i.e., Conversion Rate = 32 or 64
Conversions per Second)
OPEN-DRAIN DIGITAL OUTPUTS
(THERM, ALERT)
Output Low Voltage, VOL
High Level Output Leakage Current, IOH
0.4 V
IOUT = –6.0 mA2
0.1 1
µA
VOUT = VDD2
SMBus INTERFACE2
Logic Input High Voltage, VIH
SCLK, SDATA
Logic Input Low Voltage, VIL
Hysteresis
SCLK, SDATA
SMBus Output Low Sink Current
ALERT Output Low Sink Current
Logic Input Current, IIH, IIL
SMBus Input Capacitance, SCLK, SDATA
SMBus Clock Frequency
SMBus Timeout
SMBus Clock Low Time, tLOW
SMBus Clock High Time, tHIGH
SMBus Start Condition Setup Time, tSU:STA
SMBus Start Condition Hold Time, tHD:STA
SMBus Stop Condition Setup Time, tSU:STO
SMBus Data Valid to SCLK Rising Edge
Time, tSU:DAT
SMBus Data Hold Time, tHD:DAT
SMBus Bus Free Time, tBUF
SCLK Falling Edge to SDATA
Valid Time, tVD,DAT
SCLK, SDATA Rise Time, tR
SCLK, SDATA Fall Time, tF
2.1
V
VDD = 3 V to 5.5 V
0.8 V
VDD = 3 V to 5.5 V
500
mV
6
1
–1
5
25
4.7
4
4.7
4
4
250
300
4.7
mA SDATA Forced to 0.6 V
mA ALERT Forced to 0.4 V
+1
µA
pF
100 kHz
64
ms
Note 3
µs
tLOW between 10% Points
µs
tHIGH between 90% Points
µs
µs
Time from 10% of SDATA to 90%
of SCLK
µs
Time from 90% of SCLK to 10%
of SDATA
ns
Time for 10% or 90% of SDATA to
10% of SCLK
µs
µs
Between Start/Stop Condition
1
µs
Master Clocking in Data
1
µs
300 ns
NOTES
1See Table VI for information on other conversion rates.
2Guaranteed by Design, not production tested.
3The SMBus timeout is a programmable feature. By default it is not enabled. Details on how to enable it are available in the SMBus section of this data sheet.
Specifications subject to change without notice.
–2–
REV. 0
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