N28F001BX-T70 데이터 시트보기 (PDF) - Intel
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N28F001BX-T70 Datasheet PDF : 33 Pages
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28F001BX-T 28F001BX-B
AC CHARACTERISTICS Write Erase Program Operations(1 9)
28F001BX-70
28F001BX-90
Symbol
Parameter
VCC e 5V
Notes g5%(10)
30 pF
VCC e 5V
g10%(11)
100 pF
VCC e 5V
g10%(11)
100 pF
Units
Min Max Min Max Min Max
tAVAV tWC Write Cycle Time
70
75
90
ns
tPHWL tPS RP High Recovery to WE
2 480
480
480
ns
Going Low
tELWL tCS CE Setup to WE Going Low
10
10
10
ns
tWLWH tWP WE Pulse Width
35
40
40
ns
tPHHWH tPHS RP VHH Setup to WE Going 2 100
100
100
ns
High
tVPWH tVPS VPP Setup to WE Going High
2 100
100
100
ns
tAVWH tAS Address Setup to WE Going
3 35
40
40
ns
High
tDVWH tDS Data Setup to WE Going High
4
35
40
40
ns
tWHDX tDH Data Hold from WE High
10
10
10
ns
tWHAX tAH Address Hold from WE High
10
10
10
ns
tWHEH tCH CE Hold from WE High
10
10
10
ns
tWHWL tWPH WE Pulse Width High
35
35
35
ns
tWHQV1
Duration of Programming
5 6 7 15
15
15
ms
Operation
tWHQV2
Duration of Erase Operation
5 6 7 13
13
13
sec
(Boot)
tWHQV3
Duration of Erase Operation
5 6 7 13
13
13
sec
(Parameter)
tWHQV4
Duration of Erase Operation
5 6 7 30
30
30
sec
(Main)
tWHGL
Write Recovery before Read
0
0
0
tQVVL tVPH VPP Hold from Valid SRD
26 0
0
0
tQVPH tPHH RP VHH Hold from Valid SRD 2 7 0
0
0
tPHBR
Boot-Block Relock Delay
2
100
100
ms
ns
ns
100 ns
NOTES
1 Read timing characteristics during erase and program operations are the same as during read-only operations Refer to
AC Characteristics for Read-Only Operations
2 Sampled not 100% tested
3 Refer to Table 3 for valid AIN for byte programming or block erasure
4 Refer to Table 3 for valid DIN for byte programming or block erasure
5 The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory including byte program and verify (programming) and block precondition precondition verify erase and erase
verify (erasing)
6 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of
program erase success (SR 3 4 5 e 0)
7 For boot block programming and erasure RP should be held at VHH until determination of program erase success
(SR 3 4 5 e 0)
8 Alternate boot block access method
9 Erase Program Cycles on extended temperature products is 10 000 cycles
10 See high speed test configuration
11 See standard test configuration
23
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