N28F001BN-B120 데이터 시트보기 (PDF) - Intel
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N28F001BN-B120 Datasheet PDF : 33 Pages
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28F001BX-T 28F001BX-B
AC CHARACTERISTICS FOR CE -CONTROLLED WRITES(1)
28F001BX-70
Symbol
Parameter
VCC e 5V
Notes g5%(8)
30 pF
VCC e 5V
g10%(9)
100 pF
Min Max Min Max
tAVAV
tPHEL
tWC Write Cycle Time
tPS RP High Recovery to CE
Going Low
70
75
2 480
480
tWLEL tWS WE Setup to CE Going Low
0
0
tELEH tCP CE Pulse Width
50
55
tPHHEH tPHS RP VHH Setup to CE Going
2 100
100
High
tVPEH tVPS VPP Setup to CE Going High
2 100
100
tAVEH tAS Address Setup to CE Going
3 35
40
High
tDVEH tDS Data Setup to CE Going High
4 35
40
tEHDX tDH Data Hold from CE High
10
10
tEHAX tAH Address Hold from CE High
10
10
tEHWH tWH WE Hold from CE High
0
0
tEHEL tEPH CE Pulse Width High
20
20
tEHQV1
Duration of Programming
5 6 15
15
Operation
tEHQV2
Duration of Erase Operation
5 6 13
13
(Boot)
tEHQV3
Duration of Erase Operation
5 6 13
13
(Parameter)
tEHQV4
Duration of Erase Operation
5 6 30
30
(Main)
tEHGL
tQVVL
tQVPH
tPHBR
Write Recovery before Read
tVPH VPP Hold from Valid SRD
tPHH RP VHH Hold from Valid SRD
Boot-Block Relock Delay
0
0
25 0
0
26 0
0
2
100
100
28F001BX-90
VCC e 5V
g10%(9)
100 pF
Units
Min Max
90
ns
480
ns
0
ns
55
ns
100
ns
100
ns
40
ns
40
ns
10
ns
10
ns
0
ns
20
ns
15
ms
13
sec
13
sec
30
sec
0
ms
0
ns
0
ns
100 ns
NOTES
1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where
CE defines the write pulse width (within a longer WE timing waveform) all set-up hold and inactive WE times should
be measured relative to the CE waveform
2 Sampled not 100% tested
3 Refer to Table 3 for valid AIN for byte programming or block erasure
4 Refer to Table 3 for valid DIN for byte programming or block erasure
5 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of
program erase success (SR 3 4 5 e 0)
6 For boot block programming and erasure RP should be held at VHH until determination of program erase success
(SR 3 4 5 e 0)
7 Alternate boot block access method
8 See high speed test configuration
9 See standard text configuration
29
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