P28F001BN 데이터 시트보기 (PDF) - Intel
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P28F001BN Datasheet PDF : 33 Pages
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28F001BX-T 28F001BX-B
AC CHARACTERISTICS FOR CE -CONTROLLED WRITES(1)
Versions
Symbol
Parameter
VCC g10%
28F001BX-120 28F001BX-150
Unit
Notes Min Max Min Max
tAVAV tWC Write Cycle Time
120
150
ns
tPHEL tPS RP High Recovery to CE Going Low
2
480
480
ns
tWLEL tWS WE Setup to CE Going Low
0
0
ns
tELEH tCP CE Pulse Width
70
70
ns
tPHHEH tPHS RP VHH Setup to CE Going High
2
100
100
ns
tVPEH tVPS VPP Setup to CE Going High
2
100
100
ns
tAVEH tAS Address Setup to CE Going High
3
50
50
ns
tDVEH tDS Data Setup to CE Going High
4
50
50
ns
tEHDX tDH Data Hold from CE High
10
10
ns
tEHAX tAH Address Hold from CE High
15
15
ns
tEHWH tWH WE Hold from CE High
0
0
ns
tEHEL tEPH CE Pulse Width High
25
25
ns
tEHQV1
Duration of Programming Operation
5 6 15
15
ms
tEHQV2
Duration of Erase Operation (Boot)
5 6 13
13
sec
tEHQV3
Duration of Erase Operation (Parameter) 5 6 1 3
13
sec
tEHQV4
Duration of Erase Operation (Main)
5 6 30
30
sec
tEHGL
Write Recovery before Read
0
0
ms
tQVVL tVPH VPP Hold from Valid SRD
25
0
0
ns
tQVPH tPHH RP VHH Hold from Valid SRD
26
0
0
ns
tPHBR
Boot-Block Relock Delay
2
100
100 ns
PROM Programmer Specifications
Versions
Symbol
Parameter
VCC g10%
Notes
tGHHEL OE VHH Setup to CE Going Low
27
tEHGH OE VHH Hold from CE High
27
28F001BX-120
Min Max
480
480
28F001BX-150
Unit
Min
Max
480
ns
480
ns
NOTES
1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where
CE defines the write pulse width (within a longer WE timing waveform) all set-up hold and inactive WE times should
be measured relative to the CE waveform
2 Sampled not 100% tested
3 Refer to Table 3 for valid AIN for byte programming or block erasure
4 Refer to Table 3 for valid DIN for byte programming or block erasure
5 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of
program erase success (SR 3 4 5 e 0)
6 For boot block programming and erasure RP should be held at VHH until determination of program erase success
(SR 3 4 5 e 0)
7 Alternate boot block access method
30
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