ADP160/ADP161/ADP162/ADP163
OUTLINE DIMENSIONS
2.90 BSC
1.60 BSC
5
4
1
2
3
2.80 BSC
*0.90 MAX
0.70 MIN
1.90
BSC
0.95 BSC
*1.00 MAX
0.20
0.08
0.10 MAX
0.50
0.30
8°
SEATING
4°
0.60
PLANE
0°
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 53. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
1.000
0.965 SQ
0.925
2
1
BALL A1
IDENTIFIER
0.640
0.595
0.550
TOP VIEW
(BALL SIDE DOWN)
END VIEW
A
0.50
REF
B
BOTTOM VIEW
(BALL SIDE UP)
0.370
0.355
0.340
COPLANARITY
0.03
SEATING
PLANE
0.340
0.320
0.300
0.270
0.240
0.210
Figure 54. 4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-1)
Dimensions shown in millimeters
Data Sheet
Rev. H | Page 20 of 24