ADP1655 데이터 시트보기 (PDF) - Analog Devices
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ADP1655 Datasheet PDF : 24 Pages
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The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu-
lated using the following equation:
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric, TOL is assumed to be 10%, and
COUT is 9.528 μF at 1.8 V, as shown in Figure 35.
Substituting these values in the equation yields
CEFF = 9.528 μF × (1 − 0.15) × (1 − 0.1) = 7.288 μF
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DC BIAS VOLTAGE (V)
Figure 35. DC Bias Characteristic of a 16 V, 10 μF Ceramic Capacitor
ADP1655
To guarantee the performance of the ADP1655, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
( ) VRIPPLE =
2π× f SW
VIN
× 2× L ×COUT
=
I RIPPLE
8 × f SW × COUT
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
ESRCOUT
≤
VRIPPLE
I RIPPLE
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is 4 μF.
Rev. 0 | Page 21 of 24
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