ADSP-21365(RevA) 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21365
(Rev.:RevA)

SHARC® Processor

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Clock Input

Table 13. Clock Input

Parameter

Min

Timing Requirements

tCK

CLKIN Period

181

tCKL

CLKIN Width Low

7.51

tCKH

CLKIN Width High

7.51

tCKRF

tCCLK2

tCKJ3,4

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

CLKIN Jitter Tolerance

3.01

–250

1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

2 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.

3 Actual input jitter should be combined with ac specifications for accurate timing analysis.

4 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

333 MHz

Max

100

3

10

+250

Unit

ns

ns

ns

ns

ns

ps

CLKIN

tC K H

tCK

tCKL

Figure 8. Clock Input

Clock Signals

The ADSP-2136x can use an external clock or a crystal. See the

CLKIN pin description in Table 4 on Page 12. The user applica-

tion program can configure theADSP-2136x to use its internal

clock generator by connecting the necessary components to the

CLKIN and XTAL pins. Figure 9 shows the component connec-

tions used for a fundamental frequency crystal operating in

parallel mode.

Note that the clock rate is achieved using a 16.67 MHz crystal

and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock

speed of 266.72 MHz). To achieve the full core clock rate, pro-

grams need to configure the multiplier bits in the

PMCTL register.

tC K J

CLKIN

C1

22pF

ADSP-2136X

R1

1M⍀*

Y1

24.576MHz

XTAL

R2

47⍀*

C2

22pF

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

*TYPICAL VALUES

Figure 9. 333 MHz Operation (Fundamental Mode Crystal)

Rev. A | Page 20 of 52 | December 2006

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