ADSP-21375KSZ-ENG 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21375KSZ-ENG

SHARC® Processor

Analog Devices 

Preliminary Technical Data

Timers

The ADSP-21375 has a total of three timers: a core timer that

can generate periodic software interrupts and two general pur-

pose timers that can generate periodic interrupts and be

independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables both general

purpose timers independently.

Two Wire Interface Port (TWI)

The TWI is a bi-directional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I2C bus protocol.

The TWI master incorporates the following features:

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 7 and 10 bit addressing

• 100K bits/s and 400K bits/s data rates

• Low interrupt rate

ROM Based Security

The ADSP-21375 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal SRAM/ROM.

Additionally, the processor is not freely accessible via the JTAG

port. Instead, a unique 64-bit key, which must be scanned in

through the JTAG or Test Access Port will be assigned to each

customer. The device will ignore a wrong key. Emulation fea-

tures and external boot modes are only available after the

correct key is scanned.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the ADSP-21375 boots at system

power-up from an 8-bit EPROM via the external port, an SPI

master, an SPI slave. Booting is determined by the boot configu-

ration (BOOTCFG1–0) pins (see Table 7 on page 15). Selection

of the boot source is controlled via the SPI as either a master or

slave device, or it can immediately begin executing from ROM.

ADSP-21375

Power Supplies

The ADSP-21375 has separate power supply connections for the

internal (VDDINT), and external (VDDEXT) power supplies. The

internal supplies must meet the 1.2V requirement. The external

supply must meet the 3.3V requirement. All external supply

pins must be connected to the same power supply.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21375 pro-

cessor to monitor and control the target board processor during

emulation. Analog Devices DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor's JTAG interface ensures that the

emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

DEVELOPMENT TOOLS

The ADSP-21375 is supported with a complete set of

CROSSCORE® software and hardware development tools,

including Analog Devices emulators and VisualDSP++® devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21375.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to non intrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Rev. PrB | Page 9 of 42 | December 2005

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