ADSP-21MOD870 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
ADSP-21MOD870 Datasheet PDF : 32 Pages
| |||
ADSP-21mod870
Figure 9 shows the IDMA Control and OVLAY Registers, Fig-
ure 10 shows the bus usage during IDMA transfers, and Figure
11 shows the DMA memory maps.
IDMA OVERLAY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM(0x3FE7)
RESERVED
SET TO 0
ID DMOVLAY ID PMOVLAY
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U U U U U U U U U U U U DM(0x3FE0)
IDMAA
ADDRESS
IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
Figure 9. IDMA Control/OVLAY Registers
IDMA DATA READ/OUTPUT
(IAD 15–0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DM 16-BIT
DATAUPPER BYTE
DATALOWER BYTE
PM 24-BIT
DATAUPPER BYTE
0 0 00 00 00
DATAMIDDLE BYTE
DATALOWER BYTE
1ST
TRANSFER
2ND
TRANSFER
IDMA DATA WRITE/INPUT
(IAD 15–0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DM 16-BIT
DATAUPPER BYTE
DATALOWER BYTE
PM 24-BIT
DATAUPPER BYTE
IGNORED
DATAMIDDLE BYTE
DATALOWER BYTE
1ST
TRANSFER
2ND
TRANSFER
PAGE AND ADDRESS LATCH
15 14
PAGE
LATCH
1
0
13 12
00
11 10
00
(IAD 15–0)
98 7654
0 0 DM PAGE
3210
PM PAGE
ADDRESS
LATCH
0
ADDRESS
0 = PM
1 = DM
Figure 10. Bus Usage During IDMA Transfers
DMA
PROGRAM MEMORY
OVLAY
DMA
DATA MEMORY
OVLAY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
0x2000–
0x3FFF
0x2000–
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 4
0x2000–
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 5
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
0x0000–
0x1FFF
0x0000–
0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 4
0x0000–
0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 5
NOTE:
IDMA AND BDMA HAVE
SEPARATE DMA CONTROL REGISTERS
Figure 11. Direct Memory Access-PM and DM Memory
Maps
Bootstrap Loading (Booting)
The ADSP-21mod870 has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits.
When the MODE pins specify BDMA booting, the ADSP-
21mod870 initiates a BDMA boot sequence when reset is
released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at Address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate boot code compatible with byte memory space.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
ADSP-21mod870. The only memory address bit provided by
the processor is A0.
IDMA Port Booting
The ADSP-21mod870 can also boot programs through its In-
ternal DMA port. If Mode C = 1, Mode B = 0, and Mode A =
1, the ADSP-21mod870 boots from the IDMA port. IDMA
feature can load as much on-chip memory as desired. Program
execution is held off until data is written to on-chip program
memory location 0.
Bus Request and Bus Grant
The ADSP-21mod870 can relinquish control of the data and
address buses to an external device. When the external device
requires access to memory, it asserts the bus request (BR)
signal. If the ADSP-21mod870 is not performing an external
memory access, it responds to the active BR input in the follow-
ing processor cycle by:
• Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal and
• Halting program execution.
If Go Mode is enabled, the ADSP-21mod870 will not halt pro-
gram execution until it encounters an instruction that requires an
external memory access.
If the ADSP-21mod870 is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
–12–
REV. 0
Share Link: 