ADSP-BF537 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF537

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 9. Pin Descriptions (Continued)

Pin Name

Port H: GPIO/10/100 Ethernet

MAC (On ADSP-BF534, these

pins are GPIO only)

PH0 – GPIO/ETxD0

PH1 – GPIO/ETxD1

PH2 – GPIO/ETxD2

PH3 – GPIO/ETxD3

PH4 – GPIO/ETxEN

PH5 – GPIO/MII TxCLK/RMII

REF_CLK

PH6 – GPIO/MII PHYINT/RMII

MDINT

PH7 – GPIO/COL

PH8 – GPIO/ERxD0

PH9 – GPIO/ERxD1

PH10 – GPIO/ERxD2

PH11 – GPIO/ERxD3

PH12 – GPIO/ERxDV/TACLK5

PH13 – GPIO/ERxCLK/TACLK6

PH14 – GPIO/ERxER/TACLK7

PH15 – GPIO/MII CRS/RMII

CRS_DV

Port J: SPORT0/TWI/SPI

Select/CAN

PJ0 – MDC

Type Function

Driver

Type1

I/O GPIO/Ethernet MII or RMII Transmit D0

E

I/O GPIO/Ethernet MII or RMII Transmit D1

E

I/O GPIO/Ethernet MII Transmit D2

E

I/O GPIO/Ethernet MII Transmit D3

E

I/O GPIO/Ethernet MII or RMII Transmit Enable

E

I/O GPIO/Ethernet MII Transmit Clock/RMII Reference E

Clock

I/O GPIO/Ethernet MII PHY Interrupt/RMII

E

Management Data Interrupt

I/O GPIO/Ethernet Collision

E

I/O GPIO/Ethernet MII or RMII Receive D0

E

I/O GPIO/Ethernet MII or RMII Receive D1

E

I/O GPIO/Ethernet MII Receive D2

E

I/O GPIO/Ethernet MII Receive D3

E

I/O GPIO/Ethernet MII Receive Data Valid/Alternate E

Timer5 Input Clock

I/O GPIO/Ethernet MII Receive Clock/Alternate

E

Timer6 Input Clock

I/O GPIO/Ethernet MII or RMII Receive Error/Alternate E

Timer7 Input Clock

I/O GPIO/Ethernet MII Carrier Sense/Ethernet RMII E

Carrier Sense and Receive Data Valid

O Ethernet Management Channel Clock

E

PJ1 – MDIO

I/O Ethernet Management Channel Serial Data

E

PJ2 – SCL

I/O

PJ3 – SDA

I/O

PJ4 – DR0SEC/CANRX/TACI0 I

PJ5 – DT0SEC/CANTX/SPI SSEL7 O

PJ6 – RSCLK0/TACLK2

I/O

PJ7 – RFS0/TACLK3

I/O

PJ8 – DR0PRI/TACLK4

I

PJ9 – TSCLK0/TACLK1

I/O

PJ10 – TFS0/SPI SSEL3

I/O

PJ11 – DT0PRI/SPI SSEL2

O

TWI Serial Clock

F

TWI Serial Data

F

SPORT0 Receive Data Secondary/CAN

Receive/Timer0 Alternate Input Capture

SPORT0 Transmit Data Secondary/CAN

C

Transmit/SPI Slave Select Enable 7

SPORT0 Receive Serial Clock/Alternate Timer2 D

Clock Input

SPORT0 Receive Frame Sync/Alternate Timer3 C

Clock Input

SPORT0 Receive Data Primary/Alternate Timer4

Clock Input

SPORT0 Transmit Serial Clock/Alternate Timer1 D

Clock Input

SPORT0 Transmit Frame Sync/SPI Slave Select C

Enable 3

SPORT0 Transmit Data Primary/SPI Slave Select C

Enable 2

Pull-Up/Pull-Down

On ADSP-BF534 processors, do not

connect PJ0, and tie PJ1 to ground

On ADSP-BF534 processors, do not

connect PJ0, and tie PJ1 to ground

Rev. B | Page 21 of 68 | July 2006

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