ADSP-BF537BBCZ-5AV 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF537BBCZ-5AV

Blackfin Embedded Processor

Analog Devices 

ADSP-BF534/ADSP-BF536/ADSP-BF537

PIN DESCRIPTIONS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pin

definitions are listed in Table 9. In order to maintain maximum

functionality and reduce package size and pin count, some pins

have dual, multiplexed functions. In cases where pin function is

reconfigurable, the default state is shown in plain text, while the

alternate function is shown in italics. Pins shown with an aster-

isk after their name (*) offer high source/high sink current

capabilities.

All pins are three-stated during and immediately after reset,

with the exception of the external memory interface, asynchro-

nous and synchronous memory control, and the buffered XTAL

output pin (CLKBUF). On the external memory interface, the

control and address lines are driven high, with the exception of

CLKOUT, which toggles at the system clock rate. If BR is active

(whether or not RESET is asserted), the memory pins are also

three-stated. During hibernate, all outputs are three-stated

unless otherwise noted in Table 9.

All I/O pins have their input buffers disabled with the exception

of the pins noted in the data sheet that need pull-ups or pull-

downs if unused.

The SDA (serial data) and SCL (serial clock) pins are open drain

and therefore require a pull-up resistor. Consult version 2.1 of

the I2C specification for the proper resistor value.

Table 9. Pin Descriptions

Pin Name

Memory Interface

ADDR19–1

DATA15–0

ABE1–0/SDQM1–0

BR

BG

BGH

Asynchronous Memory Control

AMS3–0

ARDY

AOE

ARE

AWE

Synchronous Memory Control

SRAS

SCAS

SWE

SCKE

CLKOUT

SA10

SMS

Type Function

Driver

Type1

O Address Bus for Async Access

A

I/O Data Bus for Async/Sync Access

A

O Byte Enables/Data Masks for Async/Sync Access

A

I

Bus Request (This pin should be pulled high when not used.)

O Bus Grant

A

O Bus Grant Hang

A

O Bank Select (Require pull-ups if hibernate is used.)

A

I

Hardware Ready Control

O Output Enable

A

O Read Enable

A

O Write Enable

A

O Row Address Strobe

A

O Column Address Strobe

A

O Write Enable

A

O Clock Enable(Requires a pull-down if hibernate with SDRAM self-refresh is A

used.)

O Clock Output

B

O A10 Pin

A

O Bank Select

A

Rev. J | Page 19 of 68 | February 2014

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