ADV7177KS 데이터 시트보기 (PDF) - Analog Devices

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ADV7177KS

Integrated Digital CCIR-601 to PAL/NTSC Video Encoder

Analog Devices 

DISPLAY

VERTICAL BLANK

ADV7177/ADV7178

DISPLAY

622

623

624

625

1

2

3

4

5

6

7

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

21

22

23

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

320

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 19. Timing Mode 1 (PAL)

334

335

336

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD

input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is

disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge follow-

ing the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the HSYNC,

BLANK and FIELD for an odd or even field transition relative to the pixel data.

HSYNC

FIELD

BLANK

PAL = 12 * CLOCK/2

NTSC = 16 * CLOCK/2

PIXEL

DATA

Cb Y Cr Y

PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2

Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave

REV. 0

–17–

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