DS2430A/TR(2002) 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS2430A/TR Datasheet PDF : 16 Pages
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NOTES:
1) All voltages are referenced to ground.
DS2430A
2) VPUP = external pullup voltage.
3) Input load is to ground.
4) An additional reset or communication sequence cannot begin until the reset high time has expired.
5) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1ms of this falling edge.
6) VIH is a function of the external pullup resistor and VPUP.
7) Capacitance on the data pin could be 800pF when power is first applied. If a 5kW resistor is used to
pull up the data line to VPUP, 5ms after power has been applied the parasite capacitance will not affect
normal communications.
8) The Reset Low Time (tRSTL) should be restricted to a maximum of 960µs, to allow interrupt signaling;
otherwise it could mask or conceal interrupt pulses.
9) Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse.
10) The Copy Scratchpad takes 10ms maximum, during which the voltage on the 1-Wire bus must not fall
below 2.8V.
11) Depending on the 1-Wire communication speed and the bus load characteristics, the optimal pullup
resistor value will be in the 1.5kW to 5kW range.
12) The optimal sampling point for the master is as close as possible to the end time of the 15µs tRDV
period without exceeding tRDV. For the case of a Read-One Time slot, this maximizes the amount of
time for the pullup resistor to recover to a high level. For a Read-Zero Time slot, it ensures that a read
will occur before the fastest 1-Wire device(s) releases the line.
13) The duration of the low pulse sent by the master should be a minimum of 1µs with a maximum value
as short as possible to allow time for the pullup resistor to recover the line to a high level before the 1-
Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
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