AIT1042RS38P8 데이터 시트보기 (PDF) - ANADIGICS

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AIT1042RS38P8

Integrated Digital Tuner with RF and IF Gain Control

ANADIGICS 

AIT1042

MSB

Table 17: Complete Register Map

PLL2_Ref (Downconverter Reference Divider Register)

First data byte

Second data byte

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6

000 100 1000

R counter

Third data byte

5432

LSB

10

00

PLL2_Main (Downconverter Main Divider Register)

First data byte

Second data byte

Third data byte

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000

B counter

A counter

01

PLL1_Ref (Upconverter Reference Divider Register)

First data byte

Second data byte

Third data byte

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

000 100 100000

R counter

10

10

PLL1_Main (Upconverter Main Divider Register)

First data byte

Second data byte

Third data byte

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

0000

B counter

A counter

10

11

PLL_CtrlI (Control Register I)

First data byte

Second data byte

Third data byte

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0W 0 0 0 0

CPI2

0

CPI1

10 0000 0 1

PLL_CtrlII (Control Register II)

First data byte

Second data byte

Third data byte

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 10 1 100 0000 0000 000 00 10 0 1

PLL_CtrlIII (Control Register III)

First data byte

Second data byte

Third data byte

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 110000 1000 000 100 1000 1 11

Reminder: Program Control Register III last.

PRELIMINARY DATA SHEET - Rev 1.0

17

02/2009

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