IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D
ISSI ®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-8*
Min. Max.
-8.5
Min. Max.
fMAX
Clock Frequency
— 100
— 90
tKC
Cycle Time
9.5 —
10 —
tKH
Clock High Pulse Width
3.0 —
3.0 —
tKL
Clock Low Pulse Width
3.0 —
3.0 —
tKQ
Clock Access Time
—8
— 8.5
tKQX(1) Clock High to Output Invalid
2—
2—
tKQLZ(1,2) Clock High to Output Low-Z
0—
0—
tKQHZ(1,2) Clock High to Output High-Z
2 3.5
2 3.8
tOEQ
Output Enable to Output Valid — 3.5
— 3.8
tOELZ(1,2) Output Enable to Output Low-Z 0 —
0—
tOEHZ(1,2) Output Enable to Output High-Z — 3.2
— 3.8
tAS
Address Setup Time
1.8 —
1.8 —
tSS
Address Status Setup Time
1.8 —
1.8 —
tWS
Write Setup Time
1.8 —
1.8 —
tCES
Chip Enable Setup Time
1.8 —
1.8 —
tAVS
Address Advance Setup Time 1.8 —
1.8 —
tAH
Address Hold Time
0.5 —
0.5 —
tSH
Address Status Hold Time
0.5 —
0.5 —
tWH
Write Hold Time
0.5 —
0.5 —
tCEH
Chip Enable Hold Time
0.5 —
0.5 —
tAVH
Address Advance Hold Time
0.5 —
0.5 —
*This speed available only in SF version
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
-9
Min. Max.
— 66
15 —
4.0 —
4.0 —
—9
2—
0—
24
—4
0—
—4
2—
2—
2—
2—
2—
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
-10
Min. Max.
— 66
15 —
4.0 —
4.0 —
— 10
2—
0—
1.5 4.2
—5
0—
—5
2—
2—
2—
2—
2—
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
PRELIMINARY INFORMATION Rev. 00A
04/17/01