AM29LV800DB-90SC 데이터 시트보기 (PDF) - Advanced Micro Devices

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AM29LV800DB-90SC

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

PRELIMINARY

General Description

The Am29LV800D is an 8 Mbit, 3.0 volt-only

Flash memory organized as 1,048,576 bytes or

524,288 words. The device is offered in 48-ball

FBGA, 44-pin SO, and 48-pin TSOP packages.

For more information, refer to publication

number 21536. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device requires only

a single, 3.0 volt VCC supply to perform read,

program, and erase operations. A standard

EPROM programmer can also be used to program

and erase the device.

This device is manufactured using AMD’s 0.23

µm process technology, and offers all the fea-

tures and benefits of the Am29LV800B, which

was manufactured using 0.32 µm process tech-

nology.

The standard device offers access times of 70,

90, and 120 ns, allowing high speed micropro-

cessors to operate without wait states. To elim-

inate bus contention the device has separate

chip enable (CE#), write enable (WE#) and

output enable (OE#) controls.

The device requires only a single 3.0 volt

power supply for both read and write func-

tions. Internally generated and regulated volt-

ages are provided for the program and erase

operations.

The device is entirely command set compatible

with the JEDEC single-power-supply Flash

standard. Commands are written to the

command register using standard micropro-

cessor write timings. Register contents serve as

input to an internal state-machine that controls

the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase opera-

tions. Reading data out of the device is similar

to reading from other Flash or EPROM devices.

Device programming occurs by executing the

program command sequence. This initiates the

Embedded Program algorithm—an internal

algorithm that automatically times the program

pulse widths and verifies proper cell margin. The

Unlock Bypass mode facilitates faster pro-

gramming times by requiring only two write

cycles to program data instead of four.

Device erasure occurs by executing the erase

command sequence. This initiates the

Embedded Erase algorithm—an internal algo-

rithm that automatically preprograms the array

(if it is not already programmed) before exe-

cuting the erase operation. During erase, the

device automatically times the erase pulse

widths and verifies proper cell margin.

The host system can detect whether a program

or erase operation is complete by observing the

RY/BY# pin, or by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a

program or erase cycle has been completed, the

device is ready to read array data or accept

another command.

The sector erase architecture allows memory

sectors to be erased and reprogrammed without

affecting the data contents of other sectors. The

device is fully erased when shipped from the

factory.

Hardware data protection measures include

a low VCC detector that automatically inhibits

write operations during power transitions. The

hardware sector protection feature disables

both program and erase operations in any com-

bination of the sectors of memory. This can be

achieved in-system or via programming equip-

ment.

The Erase Suspend feature enables the user to

put erase on hold for any period of time to read

data from, or program data to, any sector that

is not selected for erasure. True background

erase can thus be achieved.

The hardware RESET# pin terminates any

operation in progress and resets the internal

state machine to reading array data. The

RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the

device, enabling the system microprocessor to

read the boot-up firmware from the Flash

memory.

The device offers two power-saving features.

When addresses have been stable for a specified

amount of time, the device enters the auto-

matic sleep mode. The system can also place

the device into the standby mode. Power con-

sumption is greatly reduced in both these

modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce

the highest levels of quality, reliability and cost

effectiveness. The device electrically erases

all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is pro-

grammed using hot electron injection.

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Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

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