AD8110AST 데이터 시트보기 (PDF) - Analog Devices
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AD8110AST Datasheet PDF : 28 Pages
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AD8110/AD8111
Pin Name
INxx
DATA IN
CLK
DATA OUT
UPDATE
Pin Numbers
66, 68, 70, 72, 74, 76, 78,
1, 3, 5, 7, 9, 11, 13, 15, 64
57
58
59
56
RESET
CE
SER/PAR
OUTyy
AGND
DVCC
DGND
AVEE
AVCC
AGNDxx
AVCCxx/yy
AVEExx/yy
A0
A1
A2
D0
D1
D2
D3
D4
61
60
55
41, 38, 35, 32, 29, 26, 23, 20
2, 4, 6, 8, 10, 12, 14, 16, 46
65, 67, 69, 71, 73, 75, 77
63, 79
62, 80
17, 45
18, 44
42, 39, 36, 33, 30, 27, 24, 21
43, 37, 31, 25, 22, 19
40, 34, 28, 22
54
53
52
51
50
49
48
47
PIN FUNCTION DESCRIPTIONS
Pin Description
Analog Inputs; xx = Channel Numbers 00 Through 15.
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling Edge Triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “High.”
Disable Outputs, Active “Low.”
Chip Enable, Enable “Low.” Must be “low” to clock in and latch data.
Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.
Analog Outputs yy = Channel Numbers 00 Through 07.
Analog Ground for Inputs and Switch Matrix.
+5 V for Digital Circuitry.
Ground for Digital Circuitry.
–5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected.
+5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
–5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
Parallel Data Input, TTL Compatible (Output Select LSB).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select MSB).
Parallel Data Input, TTL Compatible (Input Select LSB).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select MSB).
Parallel Data Input, TTL Compatible (Output Enable).
VCC
ESD
INPUT
ESD
AVEE
a. Analog Input
VCC
ESD
ESD
OUTPUT
1k⍀
(AD8111 ONLY)
AVEE
b. Analog Output
VCC
ESD
RESET
ESD
20k⍀
DGND
c. Reset Input
VCC
ESD
INPUT
ESD
VCC
2k⍀
ESD
ESD
OUTPUT
DGND
d. Logic Input
DGND
e. Logic Output
Figure 5. I/O Schematics
REV. 0
–7–
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