Voltage Regulators
AN8018SA
s Application Notes (continued)
[5] About logic of PWM block
The logic for channel 1 and channel 2 of this IC is reversed. Thereby an input current flatness is realized. At the
same time, noise can be suppressed to a lower level by staggering the turn on timing.
The PWM1 block turns on the output transistor during the period when the triangular wave of the OSC terminal
(pin 1) is lower than both of the FB1 (pin 5) terminal voltage and the DT1 (pin 6) terminal voltage.
The PWM2 block turns on the output transistor during the period when the triangular wave of OSC terminal
(pin 1) is higher than both of the FB2 (pin 13) terminal voltage and the DT2 (pin 12) terminal voltage.
(Refer to figure 4.)
OSC
FB1
FB2
DT1 and DT2
are omitted
Out1
(Open-collector output)
Out2
(Totem pole output)
Channel 1
Switching transistor
emitter current IE1
Channel 2
Switching transistor
collector current IC2
IE1 + IC2
VIN
SBD
+
IC2
IE1
−
SBD
Figure 4. PWM logic explanation chart
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