APT7846
CS
DCLK
DIN
BUSY
DOUT
1
8
1
S
CONTROL BITS
8
1
8
1
S
CONTROL BITS
11 10 9 8 7 6 5
43210
11 10 9
FIGURE 10. Conversion Timing , 16-Clocks per Conversion , 8-bit Bus Interface. No DCLK Delay Re-
quired with Dedicated Serial Port.
CS
DCLK
DIN
1
S)
)
)
MODE
SGL/
DIF
2,
2,
15 1
S)
)
)
MODE
SGL/
DIF
2,
2,
15 1
S ) ) )
BUSY
DOUT
11 10 9 8 7 6 5 4 3 2 1 0
FIGURE 11. Maximum Conversion Rate , 15-Clocks per Conversion.
11 10 9 8 7 6 5 4 3 2
Copyright ANPEC Electronics Corp.
12
Rev. A.6 - Dec., 2001
www.anpec.com.tw