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APW1173 데이터 시트보기 (PDF) - Anpec Electronics

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APW1173
Anpec
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APW1173 Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
APW1173
Application Description (Cont.)
Frequency Compensation (Cont.)
L
issue.
cause the phase decrease rapidly at the natural
frequency and lead the phase margin not enough to
maintain the stable status. The stable issue improved
by apply a zero in the frequency domain to increase
the phase margin.
FB PIN
VOUT
ESR
COUT
Ceramic
type
Loading
1.235V
EA
COMP PIN
RC1
CC1
CC2
Adding a resistor and a capacitor at the COMP pin is
the simplest way to generate a zero. The placement
of the components is the show of Figure-1. The
frequency of the zero is
f zero
=
1
2πRC1CC1
(10)
The relation of the zero and the natural frequency is
f zero = 0.8 f natural
(11)
Locate the zero before the natural frequency to com-
pensate the phase. The another capacitor CC2 used to
bypass the noise. In general
CC 2
=
1
10
CC1
(12)
In the other applications, use the ceramic capacitor as
the output capacitor is very popular. Because the small
dimension of the ceramic capacitor save the PCB
(Printed Circuit Board) area, the low ESR(Equivalent
Series Resistance) of the ceramic one decrease the
power dissipation of the output capacitor.But the
serious drawbacks of the ceramic one is the stable
Consider the Figure-2, find the transfer function H(s)
as:
H (s)
=
S2
SCOUT (ESR) +1
LCOUT + SCOUT (ESR)
+1
pole1,2 = 2π
1
LCOUT
zero1
=
1
2π(ESR)COUT
Q= 1
L
(ESR) COUT
The pole1 and pole2 are the conjugate roots of the
denominator and the zero1 is the root of the numerator.
Find the Q factor from the quadratic function and the
description of Q factor as above.
The frequency response of the output stage show as
Figure-3.
0db
slope=-40db/
decade
0d
-90d
-135d
-180d
phase
f
Pole1,2 Zero1
Figure-3
Copyright © ANPEC Electronics Corp.
15
Rev. A.5 - Aug., 2005
www.anpec.com.tw

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