29LV160-120 데이터 시트보기 (PDF) - Alliance Semiconductor

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29LV160-120

3W 2M x 8 / 1M x 16 - CMOS Flash EEPROM

Alliance Semiconductor 

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Test Condition

Output Load

Output Load Capacitance CL (including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

Input timing measurement reference levels

Output timing measurement reference levels

-70, -80 -90, -120 Unit

1 TTL gate

30

100

pF

5

ns

0.0-3.0

V

1.5

V

1.5

V

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Parameter

Sector erase and verify-1 time (excludes 00h programming

prior to erase)

Programming time

Chip programming time

Erase/program cycles1

1 Erase/program cycle test is not verified on each shipped unit.

Byte

Word

Limits

Min

Typical

Max

-

1.0

15

-

10

300

-

15

360

-

7.2

27

-

100,000

-

Unit

sec

µs

µs

sec

cycles

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Parameter

Input voltage with respect to VSS on A9, OE, and RESET pin

Input voltage with respect to VSS on all DQ, address, and control pins

Current

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

Min

Max

Unit

-1.0

+12.0

V

-0.5 VCC+0.5

V

-100

+100

mA

8/30/01; V.0.9.5

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