AS3910 데이터 시트보기 (PDF) - austriamicrosystems AG

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AS3910

13.56 MHz RFID Reader IC, ISO-14443 A/B

austriamicrosystems AG 

Application Information

Figure 13:

SPI Operation Patterns <A7-A6>

SPI Operation MODE Bits

When signal SEN is low, the SPI interface is in reset and SDATAO

is in tristate; when it is high, SPI interface is enabled. It is

recommended to keep signal SEN low whenever the SPI

interface is not in use. SDATAI is sampled at the falling edge of

SCLK. All communication is done in blocks of 8 bits (bytes). First

two bits of first byte transmitted after low to high transition of

SEN define SPI operation mode. Figure 13 defines possible

modes:

MODE Pattern (com. bits)

MODE

MODE

Register Address

MODE Related Data

Register Data

M1 M0 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

WRITE

Mode

0

READ

Mode

0

FIFO

Load

1

FIFO

Read

1

COMMA

ND

1

Mode

0 A5 A4 A3 A2 A1 A0 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

1 A5 A4 A3 A2 A1 A0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

0 0 0 0 0 0 0 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

0 1 1 1 1 1 1 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

1 C5 C4 C3 C2 C1 C0

ams Datasheet, Confidential: 2013-Oct [3-02]

AS3909/AS3910 – 23

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