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AS3910-BQFP 데이터 시트보기 (PDF) - austriamicrosystems AG

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AS3910-BQFP
AmsAG
austriamicrosystems AG AmsAG
AS3910-BQFP Datasheet PDF : 47 Pages
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AS3910
Data Sheet - Application Information
8.11.2 Configuration Registers
Table 12. Configuration Register 2
Address # 02: Configuration Register 2
type: RW
Bit
Name
Def.
Function
Comments
7
sing
0 1 only RFO1 driver will be used
Choose between single and differential driving of
antenna.
6
envi
0 1 input applied to RFI1 is envelope
RF envelope input
5
tf2
0
1 reduces the gain for 11 dB in first stage
after peak detector
When both bits are set there is 17 dB gain
4
tf1
0
1 reduces the gain for 6 dB in first stage after reduction in first stage
peak detector
3
osc
0 0 13.56MHz Xtal, 1 27.12MHz Xtal
Selector for crystal oscillator
2
out_cl1
0
out_cl1
out_cl0
out_cl
0
0
1
out_cl0
0
1
0
3.39MHz Selection of clock frequency on MCU_CLK
1
6.78 MHZ output. In case of “11”, MCU_CLK output is
0
13.56 MHZ permanently low.
1
1
no output
0
Not used
Note: Default setting is set at power up and after Set Default command.
Table 13. Configuration Register 3
Address # 03: Configuration Register 3 (ISO-14443A and NFC)
Bit
Name Def.
Function
7
crc_rx
0 1 receive without CRC
6
no_par
0 1 no byte parity checking
5
p_len3
0 p_len3 p_len2 p_len1 p_len0
4
p_len2
0
0
0
0
0
3
p_len1
0
0
0
0
1
-
-
-
-
2
p_len0
0
-
-
-
-
1
1
1
1
1
Not used
0
type: RW
Comments
For ISO-14443A anticollision.
reduction
0
74ns
-
-
1106ns
When set to 1 parity bits are still detected
and removed before received data is put
in FIFO, but there is no check for their
correctness
Modulation pulse reduction,
Defined in number of 13.56 MHz clock
periods
Note: Default setting is set at power up and after Set Default command.
www.austriamicrosystems.com/HF_RFID_Reader/AS3910
Revision 2.3
25 - 47

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