Figure 7-2. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
tF
tLOW
tHIGH
tLOW
SDA IN
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tAA
tDH
SDA OUT
tR
tSU.STO
tBUF
Figure 7-3. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th Bit
ACK
Note:
WORDN
(1)
tWR
Stop
Condition
Start
Condition
1. The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal
clear/write cycle.
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