SP3220ECY/TR 데이터 시트보기 (PDF) - Signal Processing Technologies
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SP3220ECY/TR Datasheet PDF : 21 Pages
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VCC = +5V
+
C1 –
–5V
+5V
+
C2 –
–5V
C4
+ – VDD Storage Capacitor
– + VSS Storage Capacitor
C3
Figure 15. Charge Pump — Phase 1
VCC = +5V
+
C1 –
+
C2 –
–10V
C4
+ – VDD Storage Capacitor
– + VSS Storage Capacitor
C3
Figure 16. Charge Pump — Phase 2
[
T
]
+6V
a) C2+
GND 1
T
GND 2
b) C2-
T
-6V
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V
Figure 17. Charge Pump Waveforms
VCC = +5V
+
C1 –
–5V
+5V
+
C2 –
–5V
C4
+ – VDD Storage Capacitor
– + VSS Storage Capacitor
C3
Figure 18. Charge Pump — Phase 3
VCC = +5V
+
C1 –
+10V
+
C2 –
C4
+ – VDD Storage Capacitor
– + VSS Storage Capacitor
C3
Figure 19. Charge Pump — Phase 4
Date: 8/22/05
Date: 8/30/05
SP3220E/EB/EU High ESD RS-232 Driver/Receiver
13 SP3220E/EB/EU High ESD RS-232 Driver/Receiver
13
© Copyright 2005 Sipex Corporation
© Copyright 2005 Sipex Corporation
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