Figure 3. Bus Timing for 2 wire communications
SCL: Serial Clock, SDA: Serial Data I/O
AT88SC25616C
Figure 4. Write Cycle Timing:
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
Note:
STOP
CONDITION
tWR(1)
START
CONDITION
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle.
Figure 5. Data Validity
DATA
CHANGE
ALLOWED
5
5017HS–SMEM–11/08