ATMEGA6450-16AI(2004) 데이터 시트보기 (PDF) - Atmel Corporation

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ATMEGA6450-16AI
(Rev.:2004)

8-bit Microcontroller with In-System Programmable Flash

Atmel Corporation 

ATmega325/3250/645/6450

Figure 11. On-chip Data SRAM Access Cycles

T1

T2

T3

clk

CPU

Address

Data

WR

Data

RD

Compute Address

Address valid

Memory Access Instruction

Next Instruction

EEPROM Data Memory

The ATmega325/3250/645/6450 contains 1/2K bytes of data EEPROM memory. It is

organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles. The access

between the EEPROM and the CPU is described in the following, specifying the

EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control

Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,

see page 270, page 274, and page 259 respectively.

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 2. A self-timing function, how-

ever, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as

minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

23. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before the next instruction is executed.

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2570A–AVR–09/04

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