ATMEGA6450-16AI(2004) 데이터 시트보기 (PDF) - Atmel Corporation

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ATMEGA6450-16AI
(Rev.:2004)

8-bit Microcontroller with In-System Programmable Flash

Atmel Corporation 

Idle Mode

ADC Noise Reduction

Mode

Power-down Mode

Power-save Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC,

USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This

sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as

internal ones like the Timer Overflow and USART Transmit Complete interrupts. If

wake-up from the Analog Comparator interrupt is not required, the Analog Comparator

can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-

tus Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is

enabled, a conversion starts automatically when this mode is entered.

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter

ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external inter-

rupts, the USI start condition detection, Timer/Counter2, and the Watchdog to continue

operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while

allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measure-

ments. If the ADC is enabled, a conversion starts automatically when this mode is

entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a

Watchdog Reset, a Brown-out Reset, a USI start condition interrupt, a Timer/Counter2

interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin

change interrupt can wake up the MCU from ADC Noise Reduction mode.

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the external Oscillator is stopped, while the external

interrupts, the USI start condition detection, and the Watchdog continue operating (if

enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start con-

dition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake

up the MCU. This sleep mode basically halts all generated clocks, allowing operation of

asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. Refer to “External Inter-

rupts” on page 76 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition

occurs until the wake-up becomes effective. This allows the clock to restart and become

stable after having been stopped. The wake-up period is defined by the same CKSEL

Fuses that define the Reset Time-out period, as described in “Clock Sources” on page

26.

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 controller is enabled, it will keep running during sleep. The device can

wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if

the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Glo-

bal Interrupt Enable bit in SREG is set.

If the Timer/Counter2 is not running, Power-down mode is recommended instead of

Power-save mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-

save mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter

34 ATmega325/3250/645/6450

2570A–AVR–09/04

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