ATMEGA48-20AI 데이터 시트보기 (PDF) - Atmel Corporation

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ATMEGA48-20AI

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user

software can poll this bit and wait for a zero before writing the next byte. When EEPE

has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the

correct address is set up in the EEAR Register, the EERE bit must be written to a logic

one to trigger the EEPROM read. The EEPROM read access takes one instruction, and

the requested data is available immediately. When the EEPROM is read, the CPU is

halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation

is in progress, it is neither possible to read the EEPROM, nor to change the EEAR

Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 3 lists the typical

programming time for EEPROM access from the CPU.

Table 3. EEPROM Programming Time

Symbol

EEPROM write

(from CPU)

Number of Calibrated RC Oscillator Cycles Typ Programming Time

26,368

3.3 ms

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling inter-

rupts globally) so that no interrupts will occur during execution of these functions. The

examples also assume that no Flash Boot Loader is present in the software. If such

code is present, the EEPROM write function must also wait for any ongoing SPM com-

mand to finish.

20 ATmega48/88/168

2545D–AVR–07/04

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