ATMEGA88V-10AUR 데이터 시트보기 (PDF) - Atmel Corporation
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ATMEGA88V-10AUR
Atmel Corporation
ATMEGA88V-10AUR Datasheet PDF : 377 Pages
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ATmega48/88/168
Figure 8-4. On-chip data SRAM access cycles.
T1
T2
T3
clk
CPU
Address
Data
WR
Data
RD
Compute address
Address valid
Memory access instruction
Next instruction
8.4 EEPROM data memory
The Atmel ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and
the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
“Memory programming” on page 285 contains a detailed description on EEPROM Programming
in SPI or Parallel Programming mode.
8.4.1
EEPROM read/write access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-2 on page 24. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See “Preventing EEPROM corruption” on page 20 for details on how to avoid problems in
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
8.4.2
Preventing EEPROM corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
20
2545T–AVR–05/11
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