AZ12010AL 데이터 시트보기 (PDF) - Arizona Microtek, Inc

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AZ12010AL

Multiply by 16, 32 Phase-Locked Loop Clock Generator

Arizona Microtek, Inc 

AZ12010

Name

REFIN

¯R¯E¯F¯O¯¯U¯T¯

CPREF

CPOUT

CPPOL

INTREF

INTSUM

INTOUT

SAWIN

¯S¯A¯W¯¯I¯N¯

SAWOUT

S¯A¯¯W¯¯O¯U¯¯T

ENABLE

DIV_SEL

Q

Q¯

VBB

VEEP

VCC

VEE

AZ12010 FUNCTIONAL PIN/PAD DESCRIPTIONS

Functional Description

Reference Frequency Input This pin/pad includes an on-chip 470 Ω pull

down resistor to VBB. The input from the reference circuit should be AC

coupled.

Reference Frequency Output This pin is an inverted and amplified version of

the signal on the REFIN pin. The gain from REFIN to ¯R¯E¯F¯O¯¯U¯T¯ is

approximately 20. If VEEP is connected to VEE, a 4 ma on-chip current source is

provided for the output.

Logic Level

PECL

¯R¯E¯F¯O¯¯U¯T¯ is not available on the packaged versions (AZ12010A, AZ12010B).

Charge Pump Reference Output The pin/pad voltage is nominally 1.2 volts

below VCC.

Charge Pump Output The charge pump output voltage is VCPREF ±0.3V

during a phase correction pulse. When there is no correction pulse the output

goes high impedance.

Charge Pump Polarity When this pin/pad is pulled high the PLL operates

with a VCSO circuit exhibiting negative pulling slope (the VCSO frequency

goes down when the control voltage goes up). When this pin/pad is pulled low

(AZM12010B) the PLL operates with a VCSO circuit exhibiting positive

pulling slope (the VCSO frequency goes up when the control voltage goes up).

If the pin/pad is left open (AZM12010A), an internal pullup resistor selects

negative pulling slope mode.

Integrator Reference Input This pin/pad should be connected to CPREF

through a bias current cancellation network

Integrator Summing Junction This pin/pad is the summing junction for the

integrator amplifier

Integrator Output

SAW Amplifier Inputs If only one input is used (Single-ended VCSO), the

unused input should be bypassed with a capacitor to VBB.

SAW Amplifier Outputs These are open collector outputs for driving the

VCSO device. Operating at nominally 9 ma, external pullup resistors must be

connected between these pins/pads and VCC. If only one output is used, the

other output should be connected to VCC through a 50Ω resistor.

PLL Output Enable The Q and Q¯ outputs are enabled when this pin/pad is

pulled high. When this pin/pad is low, the Q output is high, and the Q¯ output is

low. If the pin/pad is left open, an internal pullup resistor enables the outputs.

Divide Select When this pin/pad is high, the Q and Q¯ outputs are divided by

one from the SAW device. When it is low, the Q and Q¯ outputs are divided by

two from the SAW device. If the pin/pad is left open, an internal pullup resistor

selects the divide by one mode.

Clock Output These pin/pads are the main clock output. When ENABLE is

low, the outputs are disabled with Q high and Q¯ low.

Reference Voltage Output This pin/pad is used to bias the REFIN signal. It

must be bypassed externally to the VEE pins/pads with a 0.01 μF capacitor.

R¯¯E¯F¯O¯¯U¯T¯ Current Source If VEEP is connected to VEE, a 4 ma on-chip current

source is provided for the ¯R¯E¯F¯O¯¯U¯T¯ output.

LVCMOS

LVTTL

CML (Analog)

LVCMOS

LVTTL

LVCMOS

LVTTL

PECL

VEEP is not available on the packaged versions (AZ12010A, AZ12010B).

Positive Supply +3.0 to +3.6 V

Negative Supply Ground

November 2006 * REV - 5

www.azmicrotek.com

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