STK673-010 데이터 시트보기 (PDF) - SANYO -> Panasonic
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STK673-010 Datasheet PDF : 16 Pages
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STK673-010
Notes On Use
(1) Input terminal use of 5V system
[RESET and Clock (timing of input signal upon rising of
power supply)]
The driver is configured to include a 5V system logic sec-
tion and a 24V MOSFETs section. The MOSFETs on both
VCC1 side and GND side are N-channels. Thus, the MOS-
FETs on the VCC1 side is provided with a charging pump
circuit for generating a voltage higher than that of VCC1.
When a Low signal is input to a RESET terminal for oper-
ating the RESET, the charging pump is stopped. After the
release of the RESET (High input), it requires a period of
1.7 ms to rise the charging pump. Accordingly, even when
a Clock signal is input during the rising of the charging
pump circuit, the MOSFET cannot be operated. Such a
timing needs to be taken into consideration for inputting a
Clock signal. An example of timing is shown in Figure 1.
Figure 1. Timing chart of RESET signal and Clock signal
When the RESET terminal switches from Low to High where a High period is 1.7ms or longer and the Clock input is
conducted in a Low state, each phase current of the motor is maintained at the following values.
Phase
U phase
V phase
W phase
Current in the case where the initial Clock signal is maintained
at Low level (Other than 2-3-phase TU excitation)
0
-87% of peak current during normal rotation
+87% of peak current during normal rotation
Current in the case where the initial Clock signal is maintained
at Low level (2-3-phase TU excitation)
0
-100% of peak current during normal rotation
+100% of peak current during normal rotation
Refer to the Timing charts for operations.
[Clock]
Clock signals should be input under the following condi-
tions so that all 9 types of excitation modes shown in the
Excitation Mode Table.
Input frequency range
Minimum pulse width
High level duty
DC to 50 kHz
10 µs
40 to 60 %
When Mode C is not used, it is an operation based on ris-
ing of the Clock and thus the above-mentioned condition
of high level duty is negligible. A minimum pulse width
of 10 µs or more allows excitation operation by Mode A
and Mode B. Since the operation is based on rising and
falling of the Clock under the use of Mode C, it is most
preferable to set the high level duty to 50 % so as to obtain
uniform step-wise current widths.
[Mode A, Mode B, Mode C and TU]
These 4 terminals allow selection of excitation modes. For
specific operations, refer to Excitation Mode Table and
Timing Charts.
[Hold, CW/CCW]
Hold temporary holds the motor while a phase current of
the motor is conducted, even when there are clock inputs
of Low input.
High input releases the hold, and the motor current
changes again synchronizing with the rising of Clock sig-
nals. Refer to Timing Chart for exemplary operations.
CW/CCW switches the rotational direction of the motor.
Switching to High gives a rotational operation of CW, and
Low gives a rotation operation of CCW. The timing of
switching the rotation is synchronizes the rising of the
No. 5708—7/16
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