VSC7960W 데이터 시트보기 (PDF) - Vitesse Semiconductor

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VSC7960W

3.125Gb/s CML Limiting Amplifier with LOS Detect and Laser Driver with Automatic Power Control

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

3.125Gb/s CML Limiting Amplifier with LOS Detect

and Laser Driver with Automatic Power Control

Advance Product Information

VSC7960

Limiting Amplifier Output Level Control

The LEVEL pin adjusts the output levels to 20mA when grounded and to 16mA when left unconnected.

Figure 4: Supply Current Measurement

VCC

A ICC

IOUT

100Ω

100Ω 100Ω 100Ω

VSC7959

Supply Current (ICC and IEE)

IMOD

A IEE

VEE

Laser Driver Automatic Power Control

To ensure constant average optical power, the device utilizes an Automatic Power Control loop (APC). A

photodiode mounted in the laser package provides optical feedback to compensate for changes in average laser

output power due to changes that affect laser performance such as temperature and laser lifetime. The laser bias

current is adjusted by the APC loop according to the reference current set at APCSET_MD by an external resis-

tor. An external capacitor at CAPC controls the time constant for the APC feedback loop. The recommended

value for CAPC is 0.1uF. This value reduces pattern-dependent jitter associated with the APC feedback loop

and guarantees stability. If the APC loop cannot adjust the bias current to track the desired monitor current,

FAIL is set low.

The device may be operated with or without APC. To utilize APC, a capacitor must be connected at CAPC

(0.1uF) and a resistor must be connected at APCSET_MD to set the average optical power. For open-loop oper-

ation (no APC), a 100kΩ resistor should be connected between APCSET_MD and GND. CAPC has no effect

on open-loop operation. In both modes of operation, resistors to ground should be placed at BIASMAX and

MODSET to set the bias and modulation currents.

The device may be operated with or without APC. To utilize APC, a capacitor must be connected at CAPC

(0.1µF) and a resistor must be connected at APCSET_MD to set the average optical power. For open-loop oper-

Page 14

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52359-0, Rev 2.1

05/01/01

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