AS4LC1M16S1-10TC 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS4LC1M16S1-10TC

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

Mode register set command waveform

CLK

CMD

PRE

Or Auto Refresh

tRP

MRS

ACT

tRSC(min)

tMRD

MRS can be issued only when both banks are idle.

Precharge waveforms

Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP. The earliest assertion of the precharge

command without losing any burst data is show below.

(normal write; BL = 4)

CLK

CMD

DQ

WE

PRE

D0

D1

D2

D3

(normal read; BL = 4)

CLK

CMD

Read data

PRE

DQ(CL1)

Q0

Q1

Q2

Q3

DQ(CL2)

Q0

Q1

Q2

Q3

DQ(CL3)

Q0

Q1

Q2

Q3

Auto precharge waveforms

A10 controls the selection of auto precharge during the read or write command cycle.

CLK

(write with auto precharge; BL = 4)

CMD

DQ

CLK

WE

D0

D1

D2

D3

Auto precharge starts*

(read with auto precharge; BL = 4)

CMD

Read data

DQ(CL1)

Q0

Q1

Q2

Q3

DQ(CL2)

Q0

Q1

Q2

Q3

DQ(CL3)

Q0

Q1

Q2

Q3

Auto precharge starts*

*The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be

issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

7/5/00

ALLIANCE SEMICONDUCTOR

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