C167CS-3V 데이터 시트보기 (PDF) - Infineon Technologies
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C167CS-3V Datasheet PDF : 81 Pages
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C167CS-L16M3V
Low Power
Memory Organization
The memory space of the C167CS-3V is configured in a Von Neumann architecture
which means that code memory, data memory, registers and I/O ports are organized
within the same linear address space which includes 16 MBytes. The entire memory
space can be accessed bytewise or wordwise. Particular portions of the on-chip memory
have additionally been made directly bitaddressable.
3 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
8 KBytes of on-chip Extension RAM (XRAM), organized as two blocks of 2 KByte and
6 KByte, respectively, are provided to store user data, user stacks, or code. The XRAM
is accessed like external memory and therefore cannot be used for the system stack or
for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with
maximum speed.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the
microcontroller.
Data Sheet
15
V1.0, 2001-10
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