C167CS-L16M3V 데이터 시트보기 (PDF) - Infineon Technologies
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C167CS-L16M3V Datasheet PDF : 81 Pages
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C167CS-L16M3V
Low Power
Note: When one or both of the on-chip CAN Modules are used with the interface lines
assigned to Port 4, the CAN lines override the segment address lines and the
segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines
A21/A19 … A16. CS lines can be used to increase the total amount of
addressable external memory.
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C167CS-3V’s instructions can be
executed in just one machine cycle which requires 50 ns at 40 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16
bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
32
ROM
CPU
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr.
Instr. Reg.
4-Stage
Pipeline
MDH
MDL
Mul/Div-HW
Bit-Mask Gen
ALU
(16-bit)
Barrel - Shifter
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Context Ptr.
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr. Code Seg. Ptr.
R15
General
Purpose
Registers
R0
Figure 4 CPU Block Diagram
Data Sheet
17
16
Internal
RAM
R15
R0
16
MCB02147
V1.0, 2001-10
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