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EL5410CR 데이터 시트보기 (PDF) - Elantec -> Intersil

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EL5410CR
Elantec
Elantec -> Intersil Elantec
EL5410CR Datasheet PDF : 14 Pages
First Prev 11 12 13 14
EL5210C/EL5410C
30MHz Rail-to-Rail Input-Output Op Amps
Packages Mounted on a JEDEC JESD51-7 High
Effective Thermal Conductivity Test Board
1200
1.136W
MAX TJ=125°C
1000
1.0W
909mW
833mW
800
600
SO8
θJA=110° C/W
400
MSOP8
200
θJA=115° C/W
SO14
θJA=88° C/W
TSSOP14
θJA=100° C/W
0
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Figure 3. Package Power Dissipation vs
Ambient Temperature
Packages Mounted on a JEDEC JESD51-3 Low
Effective Thermal Conductivity Test Board
1200
MAX TJ=125°C
1000
800 833mW
SO14
θJA=120° C/W
606mW
600
400 485mW
625mW
200
MSOP8
θJA=206° C/W
TSSOP14
θJA=165° C/W
SO8
θJA=160° C/W
0
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Figure 4. Package Power Dissipation vs
Ambient Temperature
Unused Amplifiers
It is recommended that any unused amplifiers in a dual
and a quad package be configured as a unity gain fol-
lower. The inverting input should be directly connected
to the output and the non-inverting input tied to the
ground plane.
Driving Capacitive Loads
The EL5210C and EL5410C can drive a wide range of
capacitive loads. As load capacitance increases, how-
ever, the -3dB bandwidth of the device will decrease and
the peaking increase. The amplifiers drive 10pF loads in
parallel with 1kwith just 1.2dB of peaking, and 100pF
with 6.5dB of peaking. If less peaking is desired in these
applications, a small series resistor (usually between 5
and 50) can be placed in series with the output. How-
ever, this will obviously reduce the gain slightly.
Another method of reducing peaking is to add a "snub-
ber" circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values
of 150and 10nF are typical. The advantage of a snub-
ber is that it does not draw any DC load current or
reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5210C and EL5410C can provide gain at high
frequency. As with any high-frequency device, good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly rec-
ommended, lead lengths should be as short as possible
and the power supply pins must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, where the VS- pin is connected to ground, a
0.1µF ceramic capacitor should be placed from VS+ to
pin to VS- pin. A 4.7µF tantalum capacitor should then
be connected in parallel, placed in the region of the
amplifier. One 4.7µF capacitor may be used for multiple
devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are
to be used.
13

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