CDP68HC68A2M 데이터 시트보기 (PDF) - Intersil

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CDP68HC68A2M

CMOS Serial 10-Bit A/D Converter

Intersil 

CDP68HC68A2

1. A write to the MSR

2. A write to the CSR

3. A write to the SAR with ENC and/or SAE = 1

4. A read of any Data Register

The contents of Data Registers are not guaranteed following

an abort. Writing a $00 to the MSR is equivalent to a reset.

To synchronously stop conversions in Modes 2 or 3 set the

SAR to $00 (See Mode 2 and Mode 3).

Analog Inputs

Shown in Figure 5 is a simplified equivalent circuit

representing the input to the Analog to Digital Converter

through the multiplexer as seen from each AIn pin.

Due to the nature of the switched capacitor array used by the

successive approximation A/D, two important points are

noted here:

A property of capacitive input is the intrinsic sample and

hold function. This provides all that is necessary to

accurately sample a point on an input waveform within the

input bandwidth shown in the specifications (under 1.5

conversion oscillator cycles).

The input to the capacitor network appears as an RC

network with a time constant and therefore places

constraints on the source impedance. The charging time and

therefore the accuracy of the conversion will be adversely

affected by increasing the source impedance.

It is recommended to set the conversion oscillator frequency

in accordance with the input impedance in order to allow

sufficient time (the 1.5 TOSC cycles) to sample a changing

waveform through the modeled input low pass filter network

which includes the input source in a series circuit with the

internal impedance.

SIGNAL

INPUT

VCC

D1

D2

OPEN

CIRCUIT

FIGURE 5B. ANALOG INPUT DURING HOLD AND IDLE TIME

The time constant (τ) for the input network is REFFCNET.

REFF = RS + RNET, CNET = 400pF, and RNET = 50Ω.

τ = REFFCNET = (RS + 50Ω) 400pF.

8τ is required during the first 1.5 sample clock cycles to

sufficiently encode 10-bit conversion. Therefore, 1.5 TS ≥ 8τ

and TS ≥ 5.33 REFFC.

TS = 1/fSAMPLE,

then fSAMPLE ≤[5.33 (RS + 85Ω) 400pF] – 1,

fSAMPLE ≤ (4.688 × 108) ⁄ (RS + 85Ω).

For example, if RS = 1000, fSAMPLE must be less than

432kHz, and TS = 2.3µs. This yields a 10-bit conversion time

of 32µs. An internal COSC ≥ 68pF, see chart.

The maximum frequency is limited by the device

specification (see characteristics) and by the (RS) Series

input resistance:

RS ≤ [(4.688 × 108"")/fSAMPLE,] – 85Ω.

For example, for a 1MHz sample clock RS max = 385Ω.

SIGNAL

INPUT

VCC

D1

R1

C1

85Ω 400pF

D2

V

V1

2.5V

FIGURE 5A. ANALOG INPUT DURING SAMPLE TIME

12

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