CP2120 데이터 시트보기 (PDF) - Silicon Laboratories

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CP2120

SPI TO I2C BRIDGE AND GPIO PORT EXPANDER

Silicon Laboratories 

CP2120

The SPI2I2C provides additional SMBus-related timers to enable I2C protocol compatibility. Setting the I2C Bus

Free Detect enables the device to poll the SMBus lines and determine when a transfer can begin. Setting the SCL

Low Time Out detect will cause an SMBus transaction to abort if the SCL line has been held low by a device for a

period of approximately 25 ms.

Internal Register Definition 4. I2CTO2: Additional I2C Time Outs

R/W

Reserved

Bit 7

R/W

Reserved

Bit 6

R/W

Reserved

Bit 5

R/W

Reserved

Bit 4

R/W

Reserved

Bit3

R/W

Reserved

Bit 2

R/W

FREN

Bit 1

R/W

LWEN

Bit 0

Internal Register Address:

Reset Value:

Bit 1:

Bit 0:

0x09

0x00

I2C Bus Free Detect

0: Bus Free Detect Disabled

1: Bus Free Detect Enabled

I2C SCL Low Time Out Detect

0: SCL Low Time Out Detect disable

1: SCL Low Time Out Detect enable

6.3. I2C Status

The CP2120 maintains an Internal Register, I2CSTAT, which describes the current status of the I2C Interface. The

I2CSTAT register can be read at any time. The CP2120 updates I2CSTAT when an I2C transaction begins, when

an I2C transaction completes (successfully or unsuccessfully), and when a received SPI command contains errors.

It is not recommended that an SPI master poll the CP2120's I2CSTAT Internal Register to determine when an I2C

transaction has completed. The SPI master should instead watch for the INT pin to drop low, and then read the

I2CSTAT register to determine the I2C transaction results.

Rev. 1.0

15

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