CP2400 데이터 시트보기 (PDF) - Silicon Laboratories

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CP2400

128/64 SEGMENT LCD DRIVER

Silicon Laboratories 

CP2400/1/2/3

15. SMBus Interface

The SMBus I/O interface is a two-wire, bi-directional serial bus that can be used to access the internal registers

and memory on CP2401/3 devices. The SMBus is compliant with the System Management Bus Specification,

version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are

byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be

transferred at up to 1/20th of the system clock (this can be faster than allowed by the SMBus specification,

depending on the system clock used). A method of extending the clock-low duration is available to accommodate

devices with different speed capabilities on the same bus.

15.1. Supporting Documents

It is assumed the reader is familiar with or has access to the following supporting documents:

1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.

2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.

3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.

15.2. SMBus Configuration

Figure 15.1 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between

3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial

clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or

similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the

SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of

devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and

1000 ns, respectively.

VDD = 5 V

VDD = 3 V

VDD = 5 V

VDD = 3 V

Master

Device

Slave

Device 1

Slave

Device 2

SDA

SCL

Figure 15.1. Typical SMBus Configuration

104

Rev. 1.0

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