CP2400 데이터 시트보기 (PDF) - Silicon Laboratories
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CP2400 Datasheet PDF : 110 Pages
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CP2400/1/2/3
4. Pinout and Package Definitions
Table 1. CP2400/1/2/3 Pin Definitions
Name
Pin Numbers
Type
Description
48-pin
32-pin
SPI I2C SPI I2C
XTAL1 1
1
1
1
A In Crystal Input. This pin is the return for the external oscillator
driver. This pin can be overdriven by an external CMOS clock.
XTAL2 2
2
2
2 A Out Crystal Output. This pin is the excitation driver for a quartz
crystal.
VDD
3
3
3
3 Power In 1.8–3.6 V Power Supply Voltage Input.
GND
4
4
4
4
Ground
CAP
48 48 32 32 Power LCD Power Supply Voltage Output. This pin requires a 10 µF
Out decoupling capacitor.
CLK 47 47 31 31 D In CMOS clock input. This pin should not be left floating.
RST
46 46 30 30
D In Device Reset. An external source can initiate a system reset by
driving this pin low for at least 15 µs. This pin has an internal
weak pullup.
INT
45 45 29 29 D Out Interrupt Service Request. This pin provides notification to the
host. This pin is a push-pull output.
NSS
44 — 28 —
D In Slave select signal for SPI interface. This pin should not be left
floating.
MOSI 43 — 27 —
D In Master Out/Slave In data signal for SPI interface. This pin
should not be left floating.
MISO 42 — 26 — D Out Master In/Slave Out data signal for SPI interface
SCK
41 — 25 —
D In Clock signal for SPI interface. This pin should not be left
floating.
PWR
— 44 — 28
D In Allows SMBus device to enter the Ultra Low Power mode. This
pin should not be left floating.
SCL — 43 — 27 D I/O Clock signal for SMBus interface. This pin should not be left
floating.
SDA
— 42 — 26 D I/O Data signal for SMBus interface. This pin should not be left
floating.
SMBA0 — 41 — 25 D In Bit 0, SMBus Slave Address. This pin should not be left floating.
P0.0
LCD0
40 40
24 24 D I/O Bit 0, Port 0
A Out
P0.1
LCD1
39 39
23 23 D I/O Bit 1, Port 0
A Out
Rev. 1.0
17
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